Analog Devices Inc. AD9546 Dual DPLL Digitized Clock Synchronizer
Analog Devices Inc. AD9546 Dual DPLL Digitized Clock Synchronizer combines digitized clocking technology that efficiently transports and distributes clock signals in systems. Digitized clocking on the AD9546 allows the design of flexible and scalable clock transport systems with well-controlled phase (time) alignment. The AD9546 is ideal for the design of network equipment that must meet the synchronization requirements for IEEE® 1588™ boundary clocks per ITU-T G.8273.2 Class D. Additionally, digitized clocking is also relevant in applications requiring the accurate transport of frequency and phase to multiple usage endpoints, such as, distributing synchronized system reference (SYSREF) clocks to an array of ADC channels.
The ADI AD9546 Dual DPLL Digitized Clock Synchronizer supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks (ITU-T G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2).
The device offers ten clock outputs that synchronize to any one of up to eight input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references, and the analog phase-locked loops (APLLs) provide frequency translation with low jitter output clocks. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.
The AD9546 is housed in a 48-lead LFCSP (7mm × 7mm) package and operates over the -40°C to +85°C temperature range.
Features
- Digitized clock transport subsystem
- 9 independent UTS blocks (time stamp egress ports)
- 2 independent IUTS blocks (time stamp ingress ports)
- Dual DPLL synchronizes 1Hz to 750MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references
- Complies with ITU-T G.8262 and Telcordia GR-253
- Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
- Continuous frequency monitoring and reference validation for frequency deviation as low as 50ppb (5 × 10−8)
- Both DPLLs feature a 24-bit fractional divider with a 24-bit programmable modulus
- Programmable digital loop filter bandwidth: 0.0001Hz to 1850Hz
- 2 independent, programmable auxiliary NCOs (1Hz to 65,535Hz, resolution <1.37pHz), suitable for IEEE 1588
- Version 2 servo feedback in PTP applications
- Automatic and manual holdover and reference switchover, providing zero delays, hitless, or phase buildout operation
- Programmable priority-based reference switching with manual, automatic revertive, and automatic non-revertive modes supported
- 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1Hz to 500MHz)
- 2 differential or 8 single-ended input references
- Crosspoint mux interconnects reference inputs to PLLs
- Supports embedded (modulated) input/output clock signals
- Fast DPLL locking modes
- Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and
- accuracy of a TCXO or OCXO
- External EEPROM support for autonomous initialization
- Single 1.8V power supply operation with internal regulation
- Built-in temperature monitor and alarm and temperature compensation for enhanced zero delay performance
Applications
- 5G timing transport high precision synchronization
- Global positioning system (GPS), precision time protocol (PTP) (IEEE 1588), and Synchronous Ethernet (SyncE) jitter cleanup and synchronization
- Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations
- Small base station clocking (baseband and radio)
- Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
- JESD204B support for an analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
- Carrier Ethernet
Block Diagram
