Microchip Technology SAMA5D2 System-in-Package (SiP) MPU

Microchip SAMA5D2 System-in-Package (SiP) MPU offers up to 1Gb DDR2 SDRAM or 2Gb LPDDR2 SDRAM in a single package. The SAMA5D2 SiP integrates the Arm^® Cortex^®-A5 processor-based SAMA5D2 MPU with DDR2-SDRAM or LPDDR2-SDRAM. The SAMA5D2 provides high-performance and ultra-low power and features PCB routing complexity, decreasing the area and number of layers. Board design becomes easier and more robust by facilitating EMI, ESD, and signal integrity design.

The DDR2-SDRAM memory sizes and package options are 128Mb TFBGA196 and 512Mb or 1Gb TFBGA289. The LPDDR2-SDRAM memory sizes and package options are 1Gb and 2Gb TFBGA361. The smallest memory sizes/package option targets applications with a small OS or bare metal, while the more extensive options are suitable for using Linux®.

Features

Arm Cortex-A5 core
- ARMv7-A architecture
- Arm TrustZone^®
- NEON™ Media Processing Engine
- Up to 500MHz
- ETM/ETB 8 Kbytes
Memory Architecture
- Memory Management Unit
- 32KB L1 data cache, 32Kbyte L1 instruction cache
- 128KB L2 cache configurable to be used as an internal SRAM
- DDR2-SDRAM memory up to 1Gb
- LPDDR2-SDRAM memory up to 2Gb
- One 128KB scrambled internal SRAM
- One 160KB internal ROM
Peripherals
- LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB
- ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface
- Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier
- One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)
- One Pulse Density Modulation Interface Controller (PDMIC)
- One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS)
- One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface
- One 10/100 Ethernet MAC (GMAC)
- Two high-speed memory card hosts:
  - SDMMC0: SD 3.0, eMMC 4.51, 8 bits
  - SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
- Two master/slave Serial Peripheral Interfaces (SPI)
- Two Quad Serial Peripheral Interfaces (QSPI)
- Five FLEXCOMs (USART, SPI, and TWI)
- Five UARTs
- Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered transmission
- One Rx-only UART in backup area (RXLP)
- One analog comparator (ACC) in backup area
- Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS)
- Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
- One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
- One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability

Safety
- Zero-power Power-On Reset (POR) cells
- Main crystal clock failure detector
- Write-protected registers
- Integrity Check Monitor (ICM) based on SHA256
- Memory Management Unit
- Independent watchdog
System Running up to 166MHz
- Reset controller, shutdown controller, periodic interval timer, independent watchdog timer, and secure Real-Time Clock (RTC) with clock calibration
- One 600MHz to 1200MHz PLL for the system and one 480MHz PLL optimized for USB high speed
- Digital fractional PLL for audio (11.2896MHz and 12.288MHz)
- Internal low-power 12MHz RC and 32KHz typical RC
- Selectable 32.768Hz low-power oscillator and 8MHz to 24MHz oscillator
- 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers
- 64-bit Advanced Interrupt Controller (AIC)
- 64-bit Secure Advanced Interrupt Controller (SAIC)
- Three programmable external clock signals
Low-Power Modes
- Ultra-Low-Power mode with fast wake-up capability
- Low-Power Backup mode with 5KB SRAM and SleepWalking™ features
  - Wake-up from up to nine wake-up pins, UART reception, analog comparison
  - Fast wake-up capability
  - Extended Backup mode with LPDDR2/DDR2-SDRAM in Self-Refresh mode
Security
- 5Kbytes of internal scrambled SRAM:
  - 1KB non-erasable on tamper detection
  - 4KB erasable on tamper detection
- 256 bits of scrambled and erasable registers
- Up to eight tamper pins for static or dynamic intrusion detections(1)
- Environmental monitors on specific versions: temperature, voltage, frequency, and active die shield
- Secure Boot Loader
- On-the-fly AES encryption/decryption on LPDDR2/DDR2-SDRAM and QSPI memories (AESB)
- RTC including time-stamping on security intrusions
- Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
Hardware cryptography
- SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2
- AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197
- TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
- True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3
Up to 128 I/Os
- Fully programmable through set/clear registers
- Multiplexing of up to eight peripheral functions per I/O line
- Each I/O line can be assigned to a peripheral or used as a general purpose I/O
- PIO controller features a synchronous output providing up to 32 bits of data output in one write operation